1. Field of the Invention
The present invention relates to ESD protection circuits for semiconductor devices and, more particularly, to an ESD protection circuit connects between I/O pad and an I/O of the internal device circuit.
2. Description of the Prior Art
With the advent of the ULSI era in 1990s, the technique of the integrate circuit, become rapidly prompt. The most prominent features are the continued scaled down the device-feature size so as to increase multiple functions in a chip without extra increase the chip's dimension. Moreover, in either the decrease of the power consumption or the increase the product portability is even significantly prompt with the alternative of the generations. For example, the voltage level VCC in typical 0.35 .mu.m CMOS technique with the gate oxide of about 7 nm has been scaled down to 3.3V or below, but the voltage level for the IC's with the gate oxide thickness of about 14 nm is about 5V.
However, as a device scaled from one micron down to submicron or beyond, it may suffer more stringent problems. For examples, hot carriers effect, and punchthrough effects are two of the major constraints in CMOS transistor scaling. Further, parasitic resistance and capacitance in the scaled device structure are required to avoid. Another worth to most take care one is the electric static discharge problems.
As mentioned before, the gate oxide thickness of the MOS devices is decreased with the advance of the IC's technique. This decrease, relative to breakdown voltage, has resulted in the greater susceptibility for these devices come to damage from the excessive voltages such as caused by an electrostatic discharge (ESD) event. During an ESD event, charges are transferred from one or more pins of the integrated circuits into devices in a very short duration, typically less than one microsecond. The transfer charges generates voltages that are large enough to break down insulating films, e.g., gate oxides on MOSFET devices, or that can dissipate sufficient energy to cause thermal failures in the devices. Consequently, in order to deal with transient ESD pulses, an integrated circuit must incorporate protection circuits at every I/O pin.
FIG. 1A shows a conventional ESD protective circuit. It has an input terminal 10 and an output terminal 20 thereto connection internal circuits and an I/O pad 20, respectively. The ESD protective circuit includes a plurality of PMOS transistors 25 in a n-well and a plurality of NMOS transistor in a p-substrate. The PMOS transistors 25 having source terminals thereof connect to a power supply VCC, drain terminals thereof connect to the I/O pad. The NMOS transistors having drain terminals thereof connect to the I/O pad 20, and the source terminals thereof connect to ground. All the gates are connected to an input terminal 10 thereto connect the internal circuit.
To prevent a negative ESD stress pulse event, the ESD protective test is achieved by setting the contact regions, which is originally connected to VCC, to the ground. The test I/O pad 20 is received a negative ESD pulse, else pins (or I/O pad) of the IC chip to be floated include the VSS, as is shown in the FIG. 1B. In the figure, shows an equivalent circuit too. It shows a parasitic SCR structure formed when the cathode 38 is received a negative ESD stress pulse. The trigger voltage of the SCR is determined by the avalanche breakdown voltage level of the n-well to p-substrate 5. When the n-well 40 to p-substrate 5 breakdown, the generated hole injected into the p-substrate 5 cause the p-substrate voltage to increase. It is then forward biasing the emitter junction, and cause npn transistor T2 to turn on, The operation voltage then goes low to about 1.2 V to sustain a high current to remove excess charge through the SCR circuit so that the device of the internal circuit will not be damaged.
However, above PMOS FET and NMOS FET formed ESD protection circuit has some issues. For example, as more circuits and functions are integrated into a single chip, a chip may contain different power pins to supply the currents for circuit operation. The voltage levels may be VCC or VDD for different IC's. The different voltage supply levels may pull another IC to the same voltage level if the ESD protection circuit used is the form as aforementioned PMOS FET and NMOS FET ESD circuit. A forward bias p-n diode may be generated from the pad which receives a high voltage to the source terminal of the PMOS so that it pull up the voltage of the devices which is original supplied with lower voltage.
For avoiding such situation to occur, using NMOS transistors to replace the PMOS as pull-up transistor is proposed. Please refer to FIG. 2A. The ESD device can protect a positive ESD stress pulse versus VSS, denoted as +ESD/VSS, a positive ESD stress pulse versus VCC, denoted as +ESD/VCC, and a negative ESD stress pulse versus VSS, denoted as -ESD/VSS except a negative ESD stress pulse versus VCC. For illustrating such situation, a schematic cross-sectional layout for the parasitic circuit is shown in FIG. 2B. There are diodes with their p regions back in back fashion series connected. Thus for relieving the ESD stress pulse, high dissipation heat will be generated in p-substrate, as a result, the sensitive devices damage will occur,
It is therefore an object of the present invention to provide an ESD protection so as to improve aforementioned issues.